1. Technology Field
The present invention relates to a flash memory chip system, and more particularly, to a flash memory chip system with an error correcting function and an error correcting controller as well as an error correcting method thereof.
2. Description of Related Art
The rapid growth in the popularity of digital cameras, cellular phones, and MP3 players in recent years has brought about the escalated demand for storage media by consumers. A flash memory has characteristics such as data non-volatility, low power consumption, compact size, and non-mechanical structure and thus is suitable for portable applications, particularly for portable products powered by batteries. For example, a memory card is a storage device using NAND flash memory as a storage medium and is widely adopted as storage media for digital cameras, cellular phones, and MP3 players.
The NAND flash memory has the characteristic that data is written by units of pages and erased by units of blocks. Each memory cell has to be erased before being written in. The blocks may be damaged due to numerous write operations. Therefore, host controllers of hosts (e.g. digital cameras, cellular phones, and MP3 players) using NAND flash memory as storage media must have a block management function capable of managing the flash memory. However, rapid development of the flash memory technology has given rise to flash memory of even greater capacity being pushed to the market. Users of old hosts have demand for storage media of newer and bigger capacity. Generally speaking, a new flash memory requires a stronger block management function to operate, which an old host controller usually may not be able to support, however.
For example, an error correcting procedure is used in the block management function of the flash memory to correct error in the data which is read. Status of a flash memory block (e.g. whether the block is damaged) is obtained according to the results of error correction. Error correcting functions of an old host controller are generally not able to support error correcting capability required by a new generation flash memory. For example, when a host controller is, at manufacture, configured with an error correcting circuit which can detect two error bits and correct 1 error bit, the old host controller will not be able to support a new generation flash memory requiring a controller capable of correcting 4 error bits in order to operate. In view of the foregoing, there exists a demand for developing a mechanism allowing for an old host controller to provide error correcting capability required by a new generation flash memory for accesses thereof without modifying original hardware design structure.